Historical MPPs -- LCAP

[bernhold "at@at" qtp.ufl.edu]

 I probably shouldn't dispute with someone who was there, but I
 distinctly remember several talks by Clementi and Dupuis (as well as
 posters by others in the group) at a number of Sanibel meetings...
 On Nov 4  7:01pm, Roberto Gomperts wrote:
 > Even the loosely coupled model in Enrico's lab (that Graham
 > describes beneath) had fast "pipe-lined" processors (again
 something
 > close to a vector machine).
 > LCAP was a very interesting architecture. It was never meant to
 > be a "true" MPP (i.e. 100's or 1000's of processors) and it did
 > not have shared memory.
 Not strictly vector, but close (pipelined VLIW), and I think that some
 of the FPSs had MAX boards which were add-on vector units.
 I also remember a global memory system being added at some point.  All
 of the nodes had access, but I don't recall if it was simultaneous or
 serialized.
 The last incarnation of LCAP I heard about was LCAP-3090, where the
 FPSs were replaced by IBM 3090s.  They did have vector facilities in
 some of these (they were not all identical).
 I got the feeling that the LCAP systems were almost continually
 evolving, with model LCAP-1, -2, and -3090 changed only for completely
 different node hardware (FPS-164s, -264s, and IBM 3090s).
 >It is remarkable that most of the original (shared memory) paralallel
 >computers had/have vector CPUs (Alliant, Convex, Cray).
 Some new ones do too -- notably the CM-5 -- though piplining
 (super-scalar) is increasingly popular.
 --
 David Bernholdt			bernhold "at@at" qtp.ufl.edu
 Quantum Theory Project		bernhold "at@at" ufpine.bitnet
 University of Florida
 Gainesville, FL  32611		904/392 6365